Semiconductor wafer and method of producing the same

ABSTRACT

A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.

TECHNICAL FIELD

The present invention relates to a method of producing a semiconductorwafer and to a semiconductor wafer. The present invention relates inparticular to a semiconductor wafer which has high flatness except atthe outer peripheral portion of the wafer and in which, when a thinoxide film is formed on a surface of the wafer in a device fabricationprocess, the oxide film on the outer peripheral portion of the wafer canbe prevented from peeling off, and to a method of producing the same.

RELATED ART

As the integration degree of semiconductor devices has beensignificantly improved recently, the width of lines forming thesemiconductor devices has become smaller. For production of suchsemiconductor devices using a stepper, the surface of the semiconductorwafers to be exposed is required to be very flat.

Conventionally, SFQR to be described later has been used as a measure offlatness to evaluate semiconductor wafers considering the convergingeffect of a stepper on the whole part of the semiconductor wafersurface.

As a method of producing a semiconductor wafer for improving the SFQR, atechnique for improving SFQR by defining the relation between thethickness of a carrier and the thickness of a semiconductor wafer beforebeing polished, and ensuring specific machining allowance based on therelation in a polishing process using a double-side polishing apparatus,is proposed (see Patent Document 1, for example).

Further, a technique that can improve SFQR by defining the relationbetween the thickness of a carrier and the thickness of a semiconductorwafer before being polished and performing a plurality of polishingprocesses under different conditions in a polishing process using adouble-side polishing apparatus, is proposed (see Patent Document 2, forexample).

Given these circumstances, as mirror polishing techniques have beendeveloped, wafers with almost the whole wafer surface being highlyplanarized have come to be produced in recent years. Today, in devicefabrication processes, wafers with an SFQR of 50 nm or less on the edgeexclusion region (a surface on which a device is to be formed (mainsurface) extending from the wafer center position to a position 2 mminward from the edge position) have been demanded. Companies arecompeting with each other to develop wafers that are highly planarizedin a uniform manner to the outer peripheral portion as possible.

In a device fabrication process, after a thin oxide film is formed on awafer surface, the surface of the formed oxide film is generallymirror-polished by chemical mechanical polishing (CMP). However, it hasbecome evident that when a wafer highly planarized to achieve an SFQR of50 nm or less on a 2-mm edge exclusion region is used in a devicefabrication process, the oxide film on an outer peripheral portion ofwafers is peeled off in some cases. Such peeling off of an oxide film onthe outer peripheral portion of a wafer is not preferable because itwould be a factor of affecting the yield of devices.

Such a phenomenon is considered to occur, for example becausesignificantly soft polishing cloth is used in CMP performed in a devicefabrication process, which would lead to a large amount of roll-off atthe surface of the outer peripheral portion of a wafer. When a siliconwafer highly planarized to the outer periphery is used, the thickness ofthe oxide film on the outer peripheral portion becomes locally thin(peripheral sagging) due to CMP process and the locally thinned portionof the oxide film may tend to easily peel off from the wafer. Theroll-off amount of an oxide film subjected to a typical CMP process isexpressed as 200 nm or more in ESFQRmax to be described below.

Therefore, the inventor of the present invention thought of producing awafer of which outer peripheral portion is rolled off purposefully inadvance taking into consideration the roll-off amount in a CMP processof a device fabrication process, thereby preventing reduction in thethickness of an oxide film on an outer peripheral portion of a wafer inthe CMP process.

Based on the above technical ideas, the inventor first made studies onproducing wafers with the outer peripheral portion greatly rolled off ina rough polishing process performed to control the flatness of the wafersurface. Then, he found that when a mirror polishing process isperformed on a wafer such that its outer peripheral portion is greatlyrolled off in a rough polishing process, SFQR of the wafer surfaceexcept for the outer peripheral portion drops significantly (as alsodescribed in paragraph [0027] of Patent Document 2). To the contrary, itwas revealed that when a mirror polishing process is performed toimprove flatness of the wafer surface except for the outer peripheralportion, the roll-off amount of the outer peripheral portion of thewafer drops.

The present invention has been completed based on technical ideascompletely different from the conventional to roll off an outerperipheral portion of a wafer purposefully. An object of the presentinvention is to provide a wafer having increased roll-off amount at theouter peripheral portion while maintaining high flatness of the wafersurface. The present invention is aimed at achieving the above object bypurposefully mirror polishing the surface of only the outer peripheralportion of the wafer having been mirror polished.

PRIOR ART DOCUMENT Patent Document

Patent Document 1: JP 2000-235941 A

Patent Document 2: JP 2009-81186 A

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

An object of the present invention made focusing on those aspects is toprovide a semiconductor wafer making it possible to increase theroll-off amount at the outer peripheral portion to prevent the peelingoff of an oxide film on the outer peripheral portion of the wafer due toreduction in the thickness of the oxide film in a CMP process of adevice fabrication process while high flatness of the wafer surface ismaintained, and to provide a method of producing the same.

Means for Solving the Problem

In order to achieve the above object, in an invention of a method ofproducing a semiconductor wafer, a semiconductor wafer has amirror-polished main surface and an edge portion beveled and polished,and the method comprises the step of performing a first polishingprocess of polishing only an outer peripheral portion of the mainsurface to form an edge roll-off region.

Further, the edge roll-off region is preferably a region obtained bypolishing the outer peripheral portion of the main surface extendingoutward from a predetermined position within 10 mm inward from an edgeposition of the wafer.

Furthermore, in a preferred embodiment of the present invention, thefirst polishing process can be performed using a ring-shaped polishingcloth having a size corresponding to the outer peripheral portion of themain surface.

The method preferably further comprises, after the first polishingprocess, the step of forming an oxide film on the main surface andperforming a second polishing process of mirror polishing a surface ofthe oxide film, and in performing the first polishing process, aroll-off amount of the edge roll-off region is preferably determined toapproximate a roll-off amount of the oxide film surface after the secondpolishing process.

A semiconductor wafer of another invention for achieving the aboveobject includes a mirror-polished main surface, an edge portion beveledand polished, and an edge roll-off region located only at an outerperipheral portion of the main surface, wherein a flatness ESFQRmax ofthe main surface of the semiconductor wafer, including at least a partof the edge roll-off region is 200 nm or more, and a flatness SFQRmax ofthe main surface except for the edge roll-off region is 50 nm or less.

Preferably, the ESFQRmax is a value obtained by measurement from aposition 1 mm inward from the edge position of the wafer toward thecenter of the wafer, and the SFQRmax is a value obtained by measurementfrom a position 2 mm inward from the edge position of the wafer towardthe center of the wafer.

Note that the “roll-off amount” herein means a distance in the thicknessdirection between the outer edge of an edge roll-off region in a surfaceof a wafer or an oxide film and the outer edge of the flat surfacewithout roll-off. The roll-off amount is positively correlated withESFQRmax to be described later (when the flatness of the rear surfacehas the same conditions).

EFFECT OF THE INVENTION

According to the present invention, a main surface of a semiconductorwafer, which is used as a surface on which a device is to be formed(hereinafter also referred to as a device formation surface), is mirrorpolished, and then the outer peripheral portion of the main surface ofthe mirror-polished wafer is further polished, thereby forming an edgeroll-off region between the main surface and the beveled portion formedat the wafer edge. Thus, reduction in the thickness of an oxide film onthe outer peripheral portion of the wafer in a CMP process can beprevented while maintaining high flatness of the wafer surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram showing an embodiment of a method of producinga semiconductor wafer in accordance with the present invention.

FIGS. 2( a) and 2(b) are cross-sectional views each showing an endportion of a semiconductor wafer having been subjected to polishingafter an oxide film is formed on its surface. FIG. 2( a) is across-sectional view illustrating a case of using a wafer with highflatness, and FIG. 2( b) is a cross-sectional view illustrating a caseof using a rolled-off wafer.

FIGS. 3( a) to 3(c) are diagrams illustrating ESFQR and SFQR.

FIGS. 4( a) and 4(b) are diagrams illustrating a method of polishing anouter peripheral portion in Example 1. FIG. 4( a) is a cross-sectionalview schematically illustrating an apparatus for polishing an outerperipheral portion, and FIG. 4( b) is a cross-sectional view including aring-shaped polishing cloth and an edge portion of a semiconductorwafer.

FIG. 5( a) is a plot showing the distribution of SFQRmax of thesemiconductor wafer according to Example 1, and FIG. 5( b) is a plotshowing the distribution of ESFQRmax of the semiconductor waferaccording to Example 1.

FIGS. 6( a) to 6(c) are diagrams illustrating the surface profile of asemiconductor wafer in accordance with Comparative Example 1. FIG. 6( a)is a cross-sectional view including an end portion of the semiconductorwafer, and FIG. 6( b) and FIG. 6( c) are diagrams illustrating SFQRmaxand ESFQRmax, respectively.

FIGS. 7( a) to 7(c) are diagrams illustrating the surface profile of asemiconductor wafer in accordance with Comparative Example 2. FIG. 7( a)is a cross-sectional view including an end portion of the semiconductorwafer, and FIG. 7( b) and FIG. 7( c) are diagrams illustrating SFQRmaxand ESFQRmax, respectively.

FIGS. 8( a) and 8(b) are diagrams illustrating a method of polishing anouter peripheral portion in Example 2. FIG. 8( a) is a cross-sectionalview schematically illustrating an apparatus for polishing an outerperipheral portion, and FIG. 8( b) is a cross-sectional view including aring-shaped polishing cloth and an edge portion of a semiconductorwafer.

FIG. 9 is a cross-sectional view illustrating an end portion ofsemiconductor wafers according to Examples 1 and 2, and ComparativeExample 1.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will now be described withreference to the drawings.

FIG. 1 is a flow diagram illustrating one embodiment of a method ofproducing a semiconductor wafer in accordance with the presentinvention. First, a silicon single crystal ingot is sliced using a wiresaw or the like to make semiconductor wafers. An edge portion of one ofthese semiconductor wafers obtained is beveled (step S1), and then roughpolishing is performed (step S2). Rough polishing is a mirror polishingprocess for controlling the surface profile (flatness). For example, theboth surfaces of the wafer are minor-polished to be flat using adouble-side polishing apparatus provided with a carrier setting thesemiconductor wafer, and an upper plate and a lower plate forsandwiching the carrier therebetween.

Next, an outer-peripheral-portion polishing step is performed forpolishing only an outer peripheral region of a main surface of thesemiconductor wafer on which a device is to be formed, thereby faultingan edge roll-off region having a specified roll-off amount between themain surface and the beveled portion (step S3). This polishing of theouter peripheral portion is polishing of only the outer peripheralportion in an area within 10 mm, preferably within 5 mm, and morepreferably 2 mm from the edge of the semiconductor wafer.

For example, the semiconductor wafer is set on a stage rotating aboutthe center of the wafer as the rotation center. While rotating thesemiconductor wafer, a polishing member is pressed against the outerperipheral portion to polish only the outer peripheral portion. Therotation of the semiconductor wafer allows the whole outer periphery ofthe wafer to be uniformly polished with a constant width. Further, theroll-off amount can be controlled by the pressure applied when thepolishing member is pressed against the semiconductor wafer, and thepolishing time.

After that, the semiconductor wafer is further finish-polished using apolishing apparatus (step S4). The finish polishing is a mirrorpolishing process performed for controlling the surface roughness suchas haze and may be performed at least on the main surface.

The semiconductor wafer produced through the above steps can achieve alarge roll-off amount at the outer peripheral portion of the wafer whilemaintaining high flatness of the wafer surface. Therefore, using thiswafer, when an oxide film is formed on the surface thereof in a devicefabrication process and the formed oxide film is mirror-polished by CMP,reduction in the thickness of the oxide film on the outer peripheralportion of the wafer can be prevented, which inhibits peeling off of thefilm. Consequently, the yield achieved in the device fabrication processcan be improved.

This will be described with reference to FIGS. 2( a) and 2(b). FIGS. 2(a) and 2(b) are cross-sectional views each showing an end portion of asemiconductor wafer having been subjected to polishing after an oxidefilm is formed on its surface. FIG. 2( a) is a cross-sectional viewillustrating a case of using a wafer with high flatness withoutpolishing the outer peripheral portion, and FIG. 2( b) is a case ofrolling off the outer peripheral portion of a semiconductor wafer bypolishing.

As shown in FIG. 2( a), a semiconductor wafer 1 with high flatnessformed by mirror polishing has a narrow edge roll-off region 1 a and asmall roll-off amount. When an oxide film 2 is formed on this wafer 1and polishing is performed by CMP in a device fabrication process, aroll-off 2 a of the oxide film around the edge would result in thereduction of the thickness of the oxide film to cause peeling off of thefilm.

In contrast, when the outer peripheral portion of the semiconductorwafer 1 is rolled off as in FIG. 2( b), the semiconductor wafer 1 onwhich the oxide film 2 is formed is greatly rolled off at the edgeportion. Therefore, even when the oxide film 2 is subjected to CMP, thethickness of the oxide film 2 on the outer peripheral portion is notreduced. In particular, when the roll-off amount of the semiconductorwafer 1 in the outer-peripheral-portion polishing step (step S3) isdetermined so as to be equivalent to the edge roll-off amount of theoxide film 2 having been processed by CMP in the device fabricationprocess, the thickness of the oxide film 2 can be almost uniform fromthe center to the edge, and peeling off of the oxide film can bereduced. Further, when the roll-off shape of the semiconductor wafer 1in the outer-peripheral-portion polishing step (step S3) is determinedso as to correspond to the roll-off shape of the oxide film 2 havingbeen processed by CMP, a semiconductor wafer provided with the oxidefilm 2 having more uniform thickness after CMP can be obtained.

SFQR (Site Front Least Squares Range) here refers to a value obtainedabout each of the site, which is the sum of absolute values of maximumdisplacement amounts of both the positive side and the negative sidefrom a reference plane in the site which is obtained by calculation ofthe data using a least square method in the prescribed site. Thepositive side means the upper side of the wafer horizontally placed withits main surface facing upward and the negative side means the lowerside in the like manner. SFQRmax refers to a maximum value among SFQRsof all the sites on the wafer. The flatness SFQRmax defined in thepresent invention is a value obtained by measuring all the sites havinga size of 26×8 mm² using a flatness measuring apparatus (WaferSightmanufactured by KLA-Tencor).

ESFQR (Edge flatness metric, Sector based, Front surface referenced,least sQuares fit reference plane, Range of the data within sector) heremeans SFQR measured inside a fan-shaped region (sector) formed on theentire outer peripheral area of the wafer. ESFQRmax means a maximumvalue among ESFQRs of all the sectors on the wafer. ESFQRmean is a meanvalue of ESFQRs of all the sectors. ESFQR prescribed in the presentinvention is a value measured in a sector (site size) obtained bydividing the entire periphery of the wafer evenly into 72 sectors at 5°intervals, each of which has a sector length of 30 mm in the diameterdirection, by means of a flatness measuring apparatus (Wafer Sightmanufactured by KLA-Tencor corporation). Note that the edge exclusionregion here is 1 mm.

FIGS. 3( a) to 3(c) are diagrams illustrating SFQR and ESFQR. A regionused for calculating the ESFQR of a 1-mm edge exclusion region is shownin FIGS. 3( a) and 3(b). A region used for calculating the SFQR of a2-mm edge exclusion region is shown in FIGS. 3( a) and 3(c). FIG. 3( a)shows a cross-sectional view of a wafer and a diagram showing the areaof the regions used for calculating ESFQR and SFQR corresponding to thecross-sectional view. FIGS. 3( b) and 3(c) are plan views showing theshape of the regions used for calculating ESFQR and SFQR, respectively.In FIGS. 3( a) to 3(c), the edge roll-off region 1 a is formed in anarea within 2 mm from the wafer edge. SFQRmax corresponds to theflatness of a device active region of the semiconductor wafer 1, whereasESFQRmax corresponds to the flatness of the outer peripheral portionexcept for the beveled portion 3 (several hundreds μm from the edge) ofthe semiconductor wafer.

Note that, in cross-sectional views of a wafer, including FIGS. 2( a)and 2(b) and other figures, the edge roll-off region 1 a is formedbetween the main surface on which a device is to be formed and thebeveled portion 3 in the wafer. The beveled portion 3 extends in thediameter direction and the thickness direction of the wafer in a rangeof a several hundred micrometers order. Meanwhile, the edge roll-offregion has a width of several millimeters order in the diameterdirection and several tens of nanometers to several hundreds ofnanometers order in the thickness direction. Therefore, the inclinationof the beveled portion 3 with respect to the diameter direction of thewafer 1 is far greater than that of the edge roll-off region. Given thissituation, in the cross-sectional views of the wafer 1, including FIGS.2( a) and 2(b) and other figures, the wafer is significantly magnifiedin the thickness direction in order to show the edge roll-off region 1a. Accordingly, the beveled portion 3 is illustrated to be almostperpendicular to the direction of the thickness of the semiconductorwafer.

Example 1

FIGS. 4( a) and 4(b) are diagrams illustrating a method of polishing anouter peripheral portion of a wafer in Example 1. FIG. 4( a) is across-sectional view schematically illustrating an apparatus forpolishing an outer peripheral portion, and FIG. 4( b) is across-sectional view including a ring-shaped polishing cloth and an edgeportion of a semiconductor wafer.

For polishing the outer peripheral portion of the semiconductor wafer 1,the apparatus in FIG. 4( a) includes a rotation stage 4 for holding thesemiconductor wafer 1 and rotating it about the central axis, and aring-shaped polishing cloth 5 for polishing only a region extendingabout 2 mm from the edge of the wafer 1. The ring-shaped polishing cloth5 rotates in the direction opposite to the rotation direction of thewafer 1. Using the ring-shaped polishing cloth 5, the ring-shapedpolishing cloth 5 can be uniformly pressed against the outer peripheralportion of the wafer, which prevents stress from being concentrated at apart of the wafer 1.

The both surfaces of the semiconductor wafer 1 having a diameter of 300mm were mirror polished in a rough polishing step (step S2). The outerperipheral portion of the semiconductor wafer 1 was polished using theapparatus in an outer-peripheral-portion polishing step (step S3). Themain surface to be used as a device formation surface was polished for60 seconds with the use of an alkaline polishing agent containingcolloidal silica as slurry.

Thus, an edge roll-off region 1 a was formed in a region extending 2 mmfrom the edge. The main surface inside the region was not subjected tothe polishing in step S3, so that high flatness was maintained. FIGS. 5(a) and 5(b) are plots showing the distribution of SFQRmax and ESFQRmaxof the semiconductor wafer 1 of Example 1, respectively. It is shownthat semiconductor wafers having an SFQRmax of 50 nm or less with the2-mm edge exclusion region and an ESFQRmax of 200 nm or more with the1-mm edge exclusion region were produced. Note that FIGS. 5( a) and 5(b)are box plots showing the maximum value and the minimum value (the topand bottom horizontal lines), the 75% and 25% lines (the upper and lowerends of the box), and the median (the horizontal line inside the box)for data with respect to 40 samples.

FIGS. 6( a) to 6(c) are diagrams illustrating the surface profile of asemiconductor wafer 1 in accordance with Comparative Example 1. FIG. 6(a) is a partial cross-sectional view including an end portion of thesemiconductor wafer 1, and FIG. 6( b) and FIG. 6( c) are diagrams eachillustrating SFQRmax and ESFQRmax, respectively. In this ComparativeExample 1, a semiconductor wafer having a diameter of 300 mm wassubjected to double-side polishing in the rough polishing step to behighly planarized. After that, finish polishing was performed withoutpolishing the outer peripheral portion. Therefore, Comparative Example 1is different from Example 1 in that the outer-peripheral-portionpolishing step S3 was not performed.

Thus, the semiconductor wafer of Comparative Example 1 had high flatnessfrom the center to the vicinity of the beveled region, so that theSFQRmax with the 2-mm edge exclusion region was 50 nm or less. On theother hand, the ESFQRmax with the 1-mm edge exclusion region was around100 nm, which is considerably less than 200 nm. Therefore, when an oxidefilm is formed in a device fabrication process, the oxide film on theouter peripheral portion would be reduced due to the consequent smalledge roll-off amount, which could result in peeling off of the film.

FIGS. 7( a) to 7(c) are diagrams illustrating the surface profile of asemiconductor wafer 1 in accordance with Comparative Example 2. FIG. 7(a) is a cross-sectional view including an end portion of thesemiconductor wafer, and FIGS. 7( b) and 7(c) are diagrams eachillustrating SFQRmax and ESFQRmax, respectively. In this ComparativeExample 2, a semiconductor wafer having a diameter of 300 mm waspolished such that the outer peripheral portion of the wafer was to begreatly edge-rolled off through a rough polishing process. Also inComparative Example 2, finish polishing was performed without polishingthe outer peripheral portion. Thus, this comparative example is aimed atachieving a large roll-off amount by controlling the polishingconditions of a conventional rough polishing process without additionalpolishing step of polishing the outer peripheral portion.

In this case, however, other area of the semiconductor wafer 1 exceptfor the outer peripheral portion cannot have high flatness as shown inFIG. 7( a). As a result, the ESFQRmax with the 1-mm edge exclusionregion was 200 nm or more, but the SFQRmax with the 2-mm edge exclusionregion was also 50 nm or more, which reduces flatness of the mainsurface to be used as a device formation surface.

As described above, it was difficult to achieve an ESFQRmax of 200 nm ormore while maintaining an SFQRmax of 50 nm or less in ComparativeExamples 1 and 2. In other words, it was difficult to provide an edgeroll-off region with a large roll-off amount while maintaining highflatness of the main surface on which a device would be formed. Bycontrast, these two conditions can be satisfied at the same time inExample 1. Thus, reduction in the yield due to peeling off of an oxidefilm was successfully prevented while satisfying requirements for highflatness of wafers for higher integration.

Since the edge roll-off region was formed in an area extending 2 mm fromthe edge in the semiconductor wafer according to Example 1, theconditions required in a device fabrication process can be satisfied:high flatness with an SFQRmax of 50 nm with a 2-mm edge exclusionregion, and an ESFQRmax of 200 nm or more corresponding to the roll-offamount of a CMP process. Consequently, a semiconductor wafer having highflatness almost over the whole wafer surface, in which peeling off of anoxide film is less likely to occur after CMP in a device fabricationprocess can be provided.

Example 2

FIGS. 8( a) and 8(b) are diagrams illustrating a method of polishing anouter peripheral portion of a wafer 1 according to Example 2. FIG. 8( a)is a cross-sectional view schematically illustrating an apparatus forpolishing an outer peripheral portion, and FIG. 8( b) is across-sectional view including a ring-shaped polishing cloth 5 and anedge portion of the semiconductor wafer 1. Example 2 is different fromExample 1 in that a polishing cloth with which a region extending about5 mm from the wafer edge can be polished was used as the ring-shapedpolishing cloth 5, and the polishing time was 90 seconds which waslonger than that in Example 1. The structure and the implementationsteps other than the above are the same as Example 1, so the explanationwill be omitted.

According to Example 2, the rolling off may start at a position about 5mm distant from the edge of the semiconductor wafer 1 where thering-shaped polishing cloth 5 contacts the semiconductor wafer 1 asshown in FIG. 8( b).

FIG. 9 is a cross-sectional view including the edge of semiconductorwafers produced in accordance with Examples 1 and 2, and ComparativeExample 1. As mentioned above, the semiconductor wafer according toExample 1 has an edge roll-off region having a higher roll-off amountthan the semiconductor wafer according to Comparative Example 1. Howeverin FIG. 9, the width of the edge roll-off region in the radial directionin Example 1 is approximately the same as that in Comparative Example 1.On the other hand, the semiconductor wafer according to Example 2 has anedge roll-off region even wider in the radial direction and has a largerroll-off amount.

Thus, a desired size of the edge roll-off region 1 a and a desiredroll-off amount can be achieved by changing the polishing width and thepolishing time with respect to the ring-shaped polishing cloth 5.

It is to be noted that the present invention is not limited only to theabove embodiments and various changes and modifications can be madethereto. For example, double-side polishing was performed in the roughpolishing step; alternatively, only the main surface to be used as adevice formation surface may be polished. The outer peripheral portionof only the main surface on which a device would be formed was polishedin the outer-peripheral-portion polishing step; however, the outerperipheral portion of the both surfaces of the semiconductor wafer maybe polished. In addition, for a ring-shaped polishing cloth used forpolishing the outer peripheral portion, the shape of the polishing clothis not limited to a ring shape as long as the outer peripheral portioncan be locally polished.

In Examples 1 and 2, an area extending 2 mm or 5 mm from the wafer edgewas polished in the outer-peripheral-portion polishing step, but thewidth of the outer peripheral portion to be polished is not limited tothese. When the area of the outer peripheral portion to be polished iswithin 10 mm from the wafer edge, the obtained wafer can have anadequately large device formation region even excluding the edgeroll-off region.

INDUSTRIAL APPLICABILITY

According to the present invention, a main surface of a semiconductorwafer, which is used as a device active region, is mirror polished, andthen the outer peripheral portion of the main surface of themirror-polished wafer is further polished, thereby forming an edgeroll-off region between the main surface of the wafer and the beveledportion formed at the wafer edge. Thus, reduction in the thickness of anoxide film on the outer peripheral portion of the wafer in a CMP processcan be prevented while maintaining high flatness of the wafer surface.

EXPLANATION OF REFERENCE NUMERALS

1: Semiconductor wafer

1 a: Edge roll-off region (wafer)

2: Oxide film

2 a: Edge roll-off region (oxide film)

3: Beveled portion (edge position)

4: Rotation stage

5: Ring-shaped polishing cloth

1. A method of producing a semiconductor wafer, wherein a semiconductorwafer has a mirror-polished main surface and an edge portion beveled andpolished, and comprising the step of performing a first polishingprocess of polishing only an outer peripheral portion of the mainsurface to form an edge roll-off region.
 2. The method of producing asemiconductor wafer according to claim 1, wherein the edge roll-offregion is a region obtained by polishing the outer peripheral portion ofthe main surface extending outward from a predetermined position within10 mm inward from an edge position of the wafer.
 3. The method ofproducing a semiconductor wafer according to claim 1 or claim 2, whereinthe first polishing process is performed using a ring-shaped polishingcloth having a size corresponding to the outer peripheral portion of themain surface.
 4. The method of producing a semiconductor wafer accordingto any one of claim 1 or 2, further comprising, after the firstpolishing process, the step of forming an oxide film on the main surfaceand performing a second polishing process of mirror polishing a surfaceof the oxide film, and wherein, in performing the first polishingprocess, a roll-off amount of the edge roll-off region is determined toapproximate a roll-off amount of the oxide film surface after the secondpolishing process.
 5. A semiconductor wafer comprising a mirror-polishedmain surface, an edge portion beveled and polished, and an edge roll-offregion located only at an outer peripheral portion of the main surface,wherein a flatness ESFQRmax of the main surface of the semiconductorwafer, including at least a part of the edge roll-off region is 200 nmor more, and a flatness SFQRmax of the main surface except for the edgeroll-off region is 50 nm or less.
 6. The semiconductor wafer accordingto claim 5, wherein the ESFQRmax is a value obtained by measurement froma position 1 mm inward from the edge position of the wafer toward thecenter of the wafer, and the SFQRmax is a value obtained by measurementfrom a position 2 mm inward from the edge position of the wafer towardthe center of the wafer.